Synthesys — semiconductor manufacturing for frontier compute
SILICON
( For frontier compute )
AT SCALE
Illustrative views
01
//
05
300 mm wafer
( Design to silicon )
( One line )
( Every wafer traced )
( Built to ramp )
Frontier compute is not short of ideas. It is short of silicon. Designs are ready years before the capacity is. Fab, packaging and test sit in different queues, and every handoff between them costs months.
THE PROCESS
From a design file
to silicon you can ship
One line, four stages
( Fabricate )
( Package )
( Test )
( Ship )
What frontier silicon actually needs
These are the parts that decide whether a tape-out becomes a product.
The record travels with the wafer
Every lot will carry its recipe, tool history and inline metrology from first oxide to final test. Open a lot a year later and you will see exactly how it was made, or split it and change one step.
- Stored
- recipe · tool · chamber · metrology
- Export
- lot genealogy, per die
Fab, packaging and test on one line
A frontier part is a stack, not a die. Wafers will move from fabrication to 2.5D and 3D integration and on to test without leaving the building or changing owners.
- Integration
- 2.5D interposer · 3D stack
- Handoffs
- none external
Yield you can see, not a number you are told
You will get the wafer maps, the defect Pareto and the parametric data, not a single percentage on an invoice. Known-good dies will be proven before they are packaged.
- Shared
- wafer maps · defect data
- Cadence
- every lot
What the line is being built for: AI accelerators, inference silicon, high-bandwidth memory, co-packaged optics and custom compute.
A chip is a few hundred process steps that all have to go right, in order, on every wafer. We built the company around that sentence.
Capacity
Three planned ways onto the line, from a first shuttle run to volume. Capacity is agreed per engagement as the line comes up.
Shuttle
Shared run
For proving a design in real silicon before you commit to a mask set.
- Shared mask set, multi-project wafer
- Lot record and wafer maps
- Mature process only
Pilot
Dedicated lots
For a team taking first silicon through qualification.
- Every process, through frontier
- Production qualification
- Full packaging and test
Volume
Reserved bay
For products that have to ship every quarter without a gap.
- Priority dispatch
- Reserved bay and tool time
- Shared yield programme
Before you ask
You do. Your design data, your mask set and the dies made from them stay yours. We will run them; we will not reuse them, and they will be held apart from every other customer on the line.
A design at or near tape-out, the process you are targeting and a rough volume. If you are earlier than that, a specification and a floorplan are enough to start the conversation. While the line is being built, early design partners help shape the process it will run.
It will be held, not scrapped quietly. You will get the excursion report with the tool, chamber and step it happened at, the wafers affected and the disposition we recommend. The lot record makes the cause a lookup rather than an argument.
That is the point of one line. A design proven on a shuttle run will move to dedicated pilot lots on the same tools and recipes, and from pilot to volume by adding starts rather than changing fabs.
The line is designed for all three. Wafers will be able to leave as tested wafers, as known-good dies, or as packaged and tested parts, including 2.5D and 3D integrated stacks.
On a pilot or volume engagement, yes, where the tools allow it. Custom modules will be qualified alongside the baseline flow and recorded in the same lot history, so a special step does not become an untracked one.
Bring a design.
Leave with silicon.
Synthesys is building its first line and talking with early design partners now. Tell us where your design is and what it has to do. An engineer answers, not a form letter.